Faculty of Applied Science & Engineering · St. George
ECE334H1
Digital Electronics
What was the average?
B
3 GPA across 1 observed term. Most recent: Fall 2025.
How is it graded?
Not yet verified
No syllabus we can lawfully use has been verified for this course.
How confident is this?
Low
A small number of terms, so read it as a range.
From the calendar
Official source · Faculty of Applied Science & EngineeringDigital design techniques for integrated circuits. The emphasis will be on the design of logic gates at the transistor level. A number of different logic families will be described, but CMOS will be emphasized. Review of: device modeling, IC processing, and Spice simulation, simplified layout rules, inverter noise margins, transient response, and power dissipation, traditional CMOS logic design, transmission gates, RC timing approximations, input-output circuits, latches and flipflops, counters and adders, decoders and muxes, dynamic gates, SRAMs, DRAMs, and EEPROMs.
- Contact hours
- 36.6 lecture · 18.3 practical · 12.2 tutorial
- Total scheduled hours for the course, not per week.
What people actually got
Last observed Fall 20251 term observed
This is a student-contributed aggregate, not an official University of Toronto record. It is also not a measure of how hard the course is — a course average moves with who enrols in it, not only with the material.
This rests on 1 reported term. It is shown because hiding it would not make it less true, but one or two results are a datapoint, not a distribution — a single unusual cohort moves this number a long way.
What we don’t have yet
Source ledger
Report an error →| Claim | Source | Captured | Status |
|---|---|---|---|
| Course description, prerequisites, exclusions, contact hours | Faculty of Applied Science & Engineering | 2026-07-25 | public fact |
| Historical average across 1 term | Student contributions, consented | 2026-07-25 | user contributed aggregate |
Page last verified 2026-07-25. A claim whose source moves is withdrawn before it goes stale.
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